According to the fabrication of semiconductor devices or integrated circuits, dynamic random access memory (DRAM) is an important microelectronic device and it is a storage device for storing information. Typically, a DRAM cell consists of a capacitor and a comparator. The capacitor in a DRAM cell stores electrostatic charge and the comparator in the DRAM compares the voltage level in the capacitor with a standard voltage level to determine that the voltage level in the capacitor is high level or low level. In other words, the capacitor has a high-level charge storage, the data recorded in the capacitor is indicated as "1". Similarly, the capacitor has a low-level charge storage, the data recorded in the capacitor is indicated as "0".
The capacitor of a DRAM cell is fabricated on the drain region of the cell and the capacitor electrically connects to the active region of the cell by using a contact plug between the capacitor and the active region. The active region electrically connects to the bit lines of the DRAM cell by using a contact window. Consequently, the manufacture of a DRAM cell must use two etching masks, one etching mask is adapted for defining the electrical contact region of the capacitor region in order to align the capacitor region with the drain region of the cell, another etching mask is adapted for defining the capacitor node of a crown-type bottom electrode.
Referring to FIG. 6, a layout structure of a DRAM cell is shown. A DRAM has several active regions 400 that are formed on the semiconductor substrate and the active regions 400 have a square shape. Several word line regions 500 are formed on the substrate for controlling the transistors of the DRAM. Additionally, several bit line regions 100 are formed on the substrate and each of the bit line regions is protected by spacers 110 for insulating isolation. Besides, the spacers are formed from silicon nitride material. The bit line contact holes 200 are formed in interlayer dielectric layers of the DRAM and the contact holes 200 cross the bit line regions 100 and the active regions 400 for electrical coupling between the bit line regions 100 and the active regions 400.
The bit line contact holes 200 are formed on the active regions 400 and the bit line regions then refill to cover on/in the bit line contact holes 200 for electrical coupling. Nevertheless, the bit line contact holes 200 are partially covers on the active regions 400 and the bit line regions 100 are partially on the bit line contact holes 200. Thus, the bit line contact holes 200 between the bit line regions 100 and the active regions 400 is hard to be completely covered. Furthermore, the substrate between the bit line regions 100 is indicated as a capacitor regions 300, in other words, the capacitors of the DRAM are formed on the active regions 400 between the bit line regions 100 for connecting the drain regions of the DRAM. During the etching process of the capacitor regions 300, there is no good isolation reliability around the bit line contact holes 200 and it can not make sure the isolation between the capacitors and the bit lines.
The layout structure of the DRAM depicted in FIG. 6 includes two electrical contacts, the first electrical contact is located between the bit line regions and the active regions, the second electrical contact is located between the capacitors and the active regions of the DRAM. The first electrical contact is located at the contact hole regions of the bit lines and it is formed by using lithography process and the etching process to etch interlayer dielectric layers for forming contact holes exposing the partial portion of the active regions and the bit line regions. The conductive material is refilled into the contact holes to serve as the electrical connection between the bit lines and the active regions. The second electrical contact is formed by using lithography and etching process during the formation of the capacitor and the contact holes of the drain regions formed in the interlayer dielectric layer. Consequently, as the contact hole of the drain region is precisely defined in position, the electrical contacts of the drain regions have good reliability. The manufacture of the first electrical contact is to form a bit line contact hole for the connection between the bit lines and the active region and the electrical conductive material is adapted for the connection between the bit line and the active region. In prior art, the bit line region do not fully overlaps on the active region and a bad insulating isolation exists therein.
The trend of fabricating DRAM cells is to shrink the size of the cells, that is, to decrease the planar area of the cells for increasing the device integration on silicon wafers. Thus, the distance between the bit lines of DRAM is shrunken to increase the integrity of integrated circuits. As the distance between the bit lines is shrunken, the isolation reliability between the bit line regions and the contact plugs of the capacitors between the bit line regions is simultaneously degraded. At the same time, to simplify the fabrication of the DRAM is an important issue for fabricating the DRAM. Therefore, it is needed that the layout structure of the active regions and the bit line regions to improve the isolation reliability between the bit line regions and the capacitor regions, not to reduce the integrity density of the DRAM.